The present invention generally relates to semiconductor devices and, more particularly, to semiconductor memory devices having dummy active regions.
Generally, semiconductor memory devices for storing data are classified into volatile memory devices and non-volatile memory devices. The volatile memory devices lose their stored data when their power supplies are interrupted, while the non-volatile memory devices continuously hold their stored data even when their power supplies are interrupted. Therefore, the non-volatile memory devices are widely used in memory cards, mobile telecommunication systems or the like.
FIG. 1 is an ideal top plan view for explaining a part of a cell array region of a conventional NAND flash memory device.
Referring to FIG. 1, a plurality of first parallel active regions 1a are arranged on a semiconductor substrate. A plurality of parallel wordlines WL1, . . . , and WLn cross the first active regions 1a. A ground selection line GSL and a string selection line SSL cross the active regions 1a at both sides of the wordlines WL1, . . . , and WLn, respectively. The first active regions 1a adjacent to the ground selection line GSL are interconnected by a second active region 1b that is a common source line CSL. The second active region 1b is parallel with the ground selection line GSL and is located opposite to the string selection line SSL. In addition, the first active regions 1a adjacent to the string selection line SSL are exposed by bitline contact holes 3.
The first and second active regions 1a and 1b are defined in one step of a photolithography/etching process. In this case, intersections A of the first and second active regions 1a and 1b are preferably patterned at an angle of 90xc2x0, as shown in FIG. 1. However, the intersections A are substantially rounded by a proximity effect during the photolithography process, as shown in FIG. 2. Therefore, a width of an actual common source line 1bxe2x80x2 increases over that of the ideal common source line 1b. As a result, what is needed is to increase a chip size in order to maintain a minimum design rule between the actual common source line 1bxe2x80x2 and the adjacent ground selection lines GSL.
Since the intersections A are rounded, a spacing between the first active regions 1a adjacent to the actual common source line 1bxe2x80x2 is smaller than the minimum design rule. This results in the definition of an abnormal isolation region having a smaller width than the minimum design rule. Thus, in a case where a device isolation region is formed using a shallow trench isolation technique, voids 5 may be formed in the abnormal device isolation region. The voids 5 are filled with a conductive layer that is deposited to form the wordlines WL1, . . . , and WLn, the ground selection line GSL, and the string selection line SSL. Although an etch process is performed to pattern the wordlines WL1, . . . , and WLn, the ground selection line GSL, and the string selection line SSL, the conductive layer in the voids 5 may still remain. As a result, a leakage current path may be created between the ground selection line GSL and the actual common source line 1bxe2x80x2. Further, because the remaining conductive layer may act as particle sources during a subsequent cleaning process. Thus, the yield of semiconductor devices might be reduced.
In order to solve the above problems, a flash memory device was recently proposed which adopts a common source line made of a conductive layer (e.g., polysilicon layer) that is different from an active region.
FIG. 3 is a top plan view of a NAND flash memory device having a common source line made of a polysilicon layer, wherein a reference symbol xe2x80x9cMxe2x80x9d represents a main memory cell array region and a reference symbol xe2x80x9cDxe2x80x9d represents a dummy cell array region arranged around the main memory cell array region M. The dummy cell array region is provided to prevent abnormal patterns from being formed at an edge of the main memory cell array region due to a difference between pattern densities of the main memory cell array region and a peripheral circuit region surrounding the main memory cell array region. Therefore, patterns in the dummy cell array region are generally identical to those in the main memory cell array region.
Referring to FIG. 3, a plurality of parallel active regions 11a are arranged at a semiconductor substrate. The active regions 11a are arranged in the main cell array region M and extend through the dummy cell array region D. A redundancy cell region may be intervened between the main memory cell array region M and the dummy cell array region D. A plurality of parallel wordlines WL1, . . . , and WLn are disposed across the active region 11a in the main memory cell array region M. A ground selection line GSL and a string selection line SSL are arranged at both sides of the wordlines WL1, . . . , and WLn. Also, the ground selection line GSL and the string selection line SSL cross the active regions 11a. 
A common source line 15 is arranged at one side of the ground selection line GSL. The common source line 15 is made of a conductive layer (e.g., polysilicon layer) that is different from the active regions 11a. Therefore, the common source line 15 is electrically connected to the active regions 11a via common source line contact holes 13. The active regions 11a adjacent to the string selection line SSL are exposed by bitline contact holes 17.
At least one dummy wordline DWL is arranged in the dummy cell array region. One or more dummy wordlines DWL cross the active regions 11a, as shown in FIG. 3.
According to the flash memory device shown in FIG. 3, bar-shaped active regions 11a are arranged in a cell array region and are parallel with one another. A common source line 15 is made of a conductive layer that is different from an active region. As a result, the problems above-mentioned in FIG. 1 and FIG. 2 can be solved. However, if a photolithography process for defining active regions 11a is carried out to realize the flash memory device of FIG. 3 on a semiconductor substrate, abnormal patterns 11axe2x80x2 may be formed, as shown in FIG. 4.
Referring to FIG. 4, a photoresist layer is coated on a semiconductor substrate in order to define active regions 11a shown in FIG. 3. Using a photo mask for forming the active regions 11a, the photoresist layer is then exposed. The exposed photoresist layer is developed, so that photoresist patterns 11axe2x80x2 are formed on the substrate to define the active regions 11a. Ends of the photoresist patterns 11axe2x80x2 are rounded by the proximity effect, as shown in FIG. 4. Thus, adhesion between the ends of the photoresist patterns 11axe2x80x2 and the substrate may be weakened. Since the developing process essentially includes a spin process to rotate the substrate, a part of the photoresist patterns 11axe2x80x2 may be lifted from a surface of the substrate during the developing process. This leads to formation of abnormal photoresist pattern 11b, as shown in FIG. 4.
A purpose of the present invention is to provide a semiconductor device forming process that is suitable for repeatably forming reliable active regions.
Another purpose of the present invention is to provide a semiconductor device increased integration density.
In order to achieve the above purposes, the present invention provides a semiconductor memory device having a dummy active region. The semiconductor memory device includes a plurality of parallel main active regions and a dummy active region, which are arranged on a semiconductor substrate. The dummy active region connects ends of the main active regions to each other and is arranged to be perpendicular to the main active regions.
According to an aspect of the present invention, the semiconductor substrate has a main memory cell array region and a dummy cell array region surrounding the main memory cell array region. (Those skilled in the art will appreciate that, typically, plural main memory cell array regions like those shown are provided, with dummy cell array regions surrounding each such memory cell array region.) The main active regions are arranged in the main memory cell array region and extend or preferably through to the dummy cell array region. Therefore, ends of the main active regions are located in the dummy cell array region. As a result, the dummy active region is also arranged in the dummy cell array region. The main memory cell array region further includes a plurality of common source lines crossing over the main active regions. The common source lines comprise conductive layer patterns, e.g., doped polysilicon patterns, metal silicide patterns or metal patterns. Each of the common source lines is electrically connected to predetermined regions of the main active regions via common source line contact holes. Alternately, each of the common source lines may be electrically connected to the main active regions via a slit-type contact hole exposing the main active regions and device isolation layers therebetween.
The main memory cell array region may further include string selection lines arranged at both sides of the respective common source lines. The string selection lines cross over the main active regions. A ground selection line is arranged between each of the string selection lines and each of the common source lines. Also, the ground selection line crosses over the main active regions. In addition, a plurality of parallel wordlines are arranged between the ground selection line and the string selection line. Also, the wordlines cross over the main active regions. As a result, the main memory cell array region includes a plurality of NAND-type strings that are arranged 2-dimensionally.
Alternately, the main memory cell array region may include a couple of wordlines arranged between the common source lines and a plurality of bitlines electrically connected to the main active regions between the couple of the wordlines. The bitlines cross over the wordlines and the common source lines. As a result, the main memory cell array region may include a plurality of NOR-type flash cells that are arranged 2-dimensionally.
According to an embodiment of the present invention, a redundancy cell array region may intervene between the main memory cell array region and the dummy cell array region. The redundancy cell array region includes redundant cells (or redundant strings) for repairing bad cells (or bad strings) in the main memory cell array region. Alternately, the redundancy cell array region may act as a region for storing chip information. In case the present invention includes the redundancy cell array region, the main active regions are extended to the dummy cell array region through the redundancy cell array region.
According to the invention, ends of the main active regions are coupled to each other via a dummy active region. Therefore, during a photolithography process for defining both the main active regions and the dummy active region, photoresist patterns defining the main active regions are supported by a photoresist pattern defining the dummy active region. Thus, although a photolithography process including a spin process is carried out, it is possible to prevent the photoresist patterns defining the main active regions from being lifted or deformed due to a centrifugal or other lateral force incident upon their radial ends.